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Renesas Electronics /R7FA4M1AB /POEG /POEGGA

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Interpret as POEGGA

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)PIDF 0 (0)IOCF 0 (0)OSTPF 0 (0)SSF 0 (0)PIDE 0 (0)IOCE 0 (0)OSTPE 0 (0)ST 0Reserved0 (0)INV 0 (0)NFEN 0 (00)NFCS

NFCS=00, IOCF=0, OSTPE=0, PIDF=0, OSTPF=0, NFEN=0, SSF=0, PIDE=0, IOCE=0, INV=0, ST=0

Description

POEG Group A Setting Register

Fields

PIDF

Port Input Detection Flag

0 (0): No output-disable request from the GTETRGn pin has occurred

1 (1): Output-disable request from the GTETRGn pin occurred.
IOCF

Output-disable Request Detection Flag from GPT

0 (0): No output-disable request from the GPT disable request has occurred

1 (1): Output-disable request from the GPT disable request occurred.
OSTPF

Oscillation Stop Detection Flag

0 (0): No output-disable request from oscillation stop detection has occurred

1 (1): Output-disable request from oscillation stop detection occurred.
SSF

Software Stop Flag

0 (0): No output-disable request from software has occurred

1 (1): Output-disable request from software occurred.
PIDE

Port Input Detection Enable Note: Can be modified only once after a reset.

0 (0): Output-disable request from the GTETRG pins disabled

1 (1): Output-disable request from the GTETRG pins enabled.
IOCE

Output-disable Request Enable from GPT Note: Can be modified only once after a reset.

0 (0): Output-disable request from the GPT disable request disabled

1 (1): Output-disable request from the GPT disable request enabled.
OSTPE

Oscillation Stop Detection Enable Note: Can be modified only once after a reset.

0 (0): A output-disable request from the oscillation stop detection disabled.

1 (1): A output-disable request from the oscillation stop detection enabled.
ST

GTETRG Input Status Flag

0 (0): GTETRG input after filtering is 0.

1 (1): GTETRG input after filtering is 1.
Reserved

These bits are read as 00000000000. The write value should be 00000000000.
INV

GTETRG Input Reverse

0 (0): GTETRG Input

1 (1): GTETRG Input Reversed.
NFEN

Noise Filter Enable

0 (0): Filtering noise disabled

1 (1): Filtering noise enabled
NFCS

Noise Filter Clock Select

0 (00): Sampling GTETRG pin input level for three times in every PCLKB.

1 (01): Sampling GTETRG pin input level for three times in every PCLKB /8.

2 (10): Sampling GTETRG pin input level for three times in every PCLKB /32.

3 (11): Sampling GTETRG pin input level for three times in every PCLKB /128.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data